DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 60

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 Overview
Rev.1.00 Sep. 08, 2005 Page 10 of 966
REJ09B0219-0100
Classification
Bus control
Bus control
Abbreviation
BREQ
BREQO
BACK
BS-A/BS-B
AS
AH
RD
RD/WR-A
LHWR
LLWR
LUB
LLB
Pin No.
(TFP-120)
112
110
111
110/116
116
116
115
111
114
113
114
113
I/O
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Description
External bus masters request the bus by
this signal.
The internal bus masters request the bus to
access the external space in the external
bus released state.
Bus acknowledge signal which indicates
that the bus has been released.
Indicates the start of a bus cycle.
Strobe signal which indicates that the output
address on the address bus is valid when
accessing the basic bus interface or byte
control SRAM interface space.
This signal is used to hold the address
when accessing the address/data
multiplexed I/O interface space.
Strobe signal to indicates that the basic bus
interface space is being read from.
Indicates the direction (input/output) of the
data bus.
Strobe signal which indicates that the upper
byte (D15 to D8) is valid when accessing
the basic bus interface space.
Strobe signal which indicates that the lower
byte (D7 to D0) is valid when accessing the
basic bus interface space.
Strobe signal which indicates that the upper
byte (D15 to D8) is valid when accessing
the byte control SRAM interface space.
Strobe signal which indicates that the lower
byte (D7 to D0) is valid when accessing the
byte control SRAM interface space.