DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 17

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.3
8.4
8.5
8.6
8.7
8.8
8.9
Section 9 I/O Ports .............................................................................................341
9.1
8.2.6
8.2.7
8.2.8
8.2.9
Activation Sources ............................................................................................................. 317
Location of Transfer Information and DTC Vector Table ................................................. 317
Operation ........................................................................................................................... 321
8.5.1
8.5.2
8.5.3
8.5.4
8.5.5
8.5.6
8.5.7
8.5.8
8.5.9
8.5.10 DTC Bus Release Timing ..................................................................................... 334
8.5.11 DTC Priority Level Control to the CPU ............................................................... 334
DTC Activation by Interrupt.............................................................................................. 335
Examples of Use of the DTC ............................................................................................. 336
8.7.1
8.7.2
8.7.3
Interrupt Sources................................................................................................................ 339
Usage Notes ....................................................................................................................... 339
8.9.1
8.9.2
8.9.3
8.9.4
8.9.5
8.9.6
8.9.7
8.9.8
Register Descriptions ......................................................................................................... 347
9.1.1
9.1.2
DTC Transfer Count Register B (CRB)................................................................ 314
DTC enable registers A to E, G, and H (DTCERA to DTCERE, DTCERG,
and DTCERH) ...................................................................................................... 314
DTC Control Register (DTCCR) .......................................................................... 315
DTC Vector Base Register (DTCVBR)................................................................ 317
Bus Cycle Division ............................................................................................... 323
Transfer Information Read Skip Function ............................................................ 325
Transfer Information Writeback Skip Function .................................................... 326
Normal Transfer Mode ......................................................................................... 326
Repeat Transfer Mode........................................................................................... 327
Block Transfer Mode ............................................................................................ 329
Chain Transfer ...................................................................................................... 330
Operation Timing.................................................................................................. 331
Number of DTC Execution Cycles ....................................................................... 333
Normal Transfer Mode ......................................................................................... 336
Chain Transfer ...................................................................................................... 336
Chain Transfer when Counter = 0......................................................................... 337
Module Stop Mode Setting ................................................................................... 339
On-Chip RAM ...................................................................................................... 339
DMAC Transfer End Interrupt.............................................................................. 339
DTCE Bit Setting.................................................................................................. 339
Chain Transfer ...................................................................................................... 340
Transfer Information Start Address, Source Address,
and Destination Address ....................................................................................... 340
Transfer Information Modification ....................................................................... 340
Endian Format....................................................................................................... 340
Data Direction Register (PnDDR) (n = 1, 2, 6, A, B, D to F, H, I, and M)........... 348
Data Register (PnDR) (n = 1, 2, 6, A, B, D to F, H, I, and M) ............................. 349
Rev.1.00 Sep. 08, 2005 Page xv of xlviiil