DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 257
DF61654N50FTV
Manufacturer Part Number
DF61654N50FTV
Description
IC H8SX/1654 MCU FLASH 120TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.DF61653N50FTV.pdf
(1020 pages)
Specifications of DF61654N50FTV
Core Processor
H8SX
Core Size
32-Bit
Speed
50MHz
Connectivity
I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
75
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
120-TQFP, 120-VQFP
For Use With
HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF61654N50FTV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 257 of 1020
- Download datasheet (6Mb)
6.9.10
For DMAC single address transfers, the DACK signal assert timing can be modified by using the
DKC bit in BCR1.
Figure 6.36 shows the DACK signal output timing. Setting the DKC bit to 1 asserts the DACK
signal a half cycle earlier.
DACK Signal Output Timing
RDNn = 0
RDNn = 1
DACK
B
Address bus
CSn
AH
RD
D15 to D0
RD
D15 to D0
BS
RD/WR
DKC = 0
DKC = 1
Figure 6.36 DACK Signal Output Timing
Note: n = 3 to 7
T
ma1
Address cycle
Address
Address
T
ma2
Rev.1.00 Sep. 08, 2005 Page 207 of 966
Data cycle
T
1
Section 6 Bus Controller (BSC)
Read
data
Read data
T
2
REJ09B0219-0100
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