DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 897

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note:
Bit
6
5
4
3
2
1
0
X: Don't care
Bit Name
PCK2
PCK1
PCK0

BCK2
BCK1
BCK0
Initial
Value
0
1
0
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Peripheral Module Clock (Pφ) Select
These bits select the frequency of the peripheral
module clock. The ratio to the input clock is as follows:
PCK (2:0) MD_CLK = 0
000:
001:
010:
011:
1XX:
The frequency of the peripheral module clock should be
lower than that of the system clock. Though these bits
can be set so as to make the frequency of the
peripheral module clock higher than that of the system
clock, the clocks will have the same frequency in reality.
Reserved
Although this bit is readable/writable, only 0 should be
written to.
External Bus Clock (Bφ) Select
These bits select the frequency of the external bus
clock. The ratio to the input clock is as follows:
BCK (2:0) MD_CLK = 0
000:
001:
010:
011:
1XX:
The frequency of the external bus clock should be lower
than that of the system clock. Though these bits can be
set so as to make the frequency of the external bus
clock higher than that of the system clock, the clocks
will have the same frequency in reality.
Setting prohibited
Setting prohibited
× 4
× 2
× 1
× 1/2
× 4
× 2
× 1
× 1/2
Rev.1.00 Sep. 08, 2005 Page 847 of 966
Section 21 Clock Pulse Generator
MD_CLK = 1
× 2
× 1
× 1/2
Setting prohibited
MD_CLK = 1
× 2
× 1
× 1/2
Setting prohibited
REJ09B0219-0100