DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 740

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 USB Function Module (USB)
15.5.7
Rev.1.00 Sep. 08, 2005 Page 690 of 966
REJ09B0219-0100
Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an
EP3 Interrupt-In Transfer
operation flow in which, if there is data to be transferred, the EP3 DE bit in the data status register is
referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Data transmission to host
Set EP3 transmission
(IFR1.EP3 TS = 1)
IN token reception
Figure 15.17 Operation of EP3 Interrupt-In Transfer
USB function
complete flag
in EP3FIFO?
Valid data
Yes
ACK
NACK
No
Interrupt request
Clear EP3 transmission
Write data to EP3 data
Write data to EP3 data
(TRG.EP3 PKTE = 1)
Write 1 to EP3 packet
Write 1 to EP3 packet
(TRG.EP3 PKTE = 1)
(IFR1.EP3 TS = 0)
register (EPDR3)
register (EPDR3)
for transmission
for transmission
complete flag
Is there data
Is there data
enable bit
enable bit
to host?
to host?
Application
Yes
Yes
No
No