DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 912

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 Power-Down Modes
22.3
Multi-Clock Function
When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, a transition is
made to multi-clock mode at the end of the bus cycle. In multi-clock mode, the CPU and bus
masters operate on the operating clock specified by bits ICK2 to ICK0. The peripheral modules
operate on the operating clock specified by bits PCK2 to PCK0. The external bus operates on the
operating clock specified by bits BCK2 to BCK0.
Even if the frequencies specified by bits PCK2 to PCK0 and BCK2 to BCK0 are higher than the
frequency specified by bits ICK2 to ICK0, the specified values are not reflected in the peripheral
module and external bus clocks. The peripheral module and external bus clocks are restricted to
the operating clock specified by bits ICK2 to ICK0.
Multi-clock mode is cleared by clearing all of bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to
BCK0 to 0. A transition is made to normal mode at the end of the bus cycle, and multi-clock mode
is cleared.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, this LSI enters
sleep mode. When sleep mode is cleared by an interrupt, multi-clock mode is restored.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, this LSI enters
software standby mode. When software standby mode is cleared by an external interrupt, multi-
clock mode is restored.
When the RES pin is driven low, the reset state is entered and multi-clock mode is cleared. The
same applies to a reset caused by watchdog timer overflow.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Rev.1.00 Sep. 08, 2005 Page 862 of 966
REJ09B0219-0100