DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 925

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 22 Power-Down Modes
22.10
Usage Notes
22.10.1 I/O Port Status
In software standby mode, the I/O port states are retained. Therefore, there is no reduction in
current consumption for the output current when a high-level signal is output.
22.10.2 Current Consumption during Oscillation Settling Standby Period
Current consumption increases during the oscillation settling standby period.
22.10.3 Module Stop Mode of DMAC or DTC
Depending on the operating state of the DMAC and DTC, bits MSTPA13 and MSTPA12 may not
be set to 1, respectively. The module stop mode setting for the DMAC or DTC should be carried
out only when the DMAC or DTC is not activated.
For details, refer to section 7, DMA Controller (DMAC), and section 8, Data Transfer Controller
(DTC).
22.10.4 On-Chip Peripheral Module Interrupts
Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module
stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU
interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled
before entering module stop mode.
22.10.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC
MSTPCRA, MSTPCRB, and MSTPCRC should only be written to by the CPU.
Rev.1.00 Sep. 08, 2005 Page 875 of 966
REJ09B0219-0100