DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 373

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 8.3
Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer
8.5.1
When the transfer data size is word and the SAR and DAR values are not a multiple of 2, the bus
cycle is divided and the transfer data is read from or written to in bytes. Similarly, when the
transfer data size is longword and the SAR and DAR values are not a multiple of 4, the bus cycle
is divided and the transfer data is read from or written to in words.
Table 8.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and
access data size. Figure 8.5 shows the bus cycle division example.
Table 8.4
CHNE CHNS DISEL
0
0
0
1
1
1
1
SAR and DAR Values Byte (B)
Address 4n
Address 2n + 1
Address 4n + 2
2. When the contents of the CRAH is written to the CRAL in repeat transfer mode



0
1
1
1
Bus Cycle Division
mode
1st Transfer
Chain Transfer Conditions
Number of Bus Cycle Divisions and Access Size
0
0
1

0

1
Transfer
Counter*
Not 0
0*

Not 0
0*
Not 0
1 (B)
1 (B)
1 (B)
2
2
1
CHNE CHNS DISEL



0
0
0

0
0
0












2nd Transfer
1 (W)
2 (B-B)
1 (W)
Word (W)
Specified Data Size



0
0
1
0
0
1

Section 8 Data Transfer Controller (DTC)
Rev.1.00 Sep. 08, 2005 Page 323 of 966
Transfer
Counter*



Not 0
0*


Not 0
0*

2
2
1
DTC Transfer
Ends at 1st transfer
Ends at 1st transfer
Interrupt request to CPU
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Ends at 2nd transfer
Ends at 2nd transfer
Interrupt request to CPU
Ends at 1st transfer
Interrupt request to CPU
Longword (LW)
1 (LW)
3 (B-W-B)
2 (W-W)
REJ09B0219-0100