DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 67

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward-
compatible with the H8/300, H8/300H, and H8S CPUs.
The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space,
and is ideal for a realtime control system.
2.1
• Upward-compatible with H8/300, H8/300H, and H8S CPUs
• Sixteen 16-bit general registers
• 87 basic instructions
• Eleven addressing modes
CPUSX10A_000120030800
 Can execute H8/300, H8/300H, and H8S/2000 object programs
 Also usable as sixteen 8-bit registers or eight 32-bit registers
 8/16/32-bit arithmetic and logic instructions
 Multiply and divide instructions
 Bit field transfer instructions
 Powerful bit-manipulation instructions
 Bit condition branch instructions
 Multiply-and-accumulate instruction
 Register direct [Rn]
 Register indirect [@ERn]
 Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)]
 Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B),
 Register indirect with pre-/post-increment or pre-/post-decrement [@+ERn, @−ERn,
 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
 Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32]
 Program-counter relative [@(d:8,PC) or @(d:16,PC)]
 Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or
 Memory indirect [@@aa:8]
 Extended memory indirect [@@vec:7]
@(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)]
@ERn+, or @ERn−]
@(ERn.L,PC)]
Features
Section 2 CPU
Rev.1.00 Sep. 08, 2005 Page 17 of 966
REJ09B0219-0100
Section 2 CPU