DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 614

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Serial Communication Interface (SCI, IrDA, CRC)
Note:
Rev.1.00 Sep. 08, 2005 Page 564 of 966
REJ09B0219-0100
Bit
3
2
1
0
*
Bit Name
PER
TEND
MPB
MPBT
Only 0 can be written, to clear the flag.
Initial
Value
0
1
0
0
R/W
R/(W)* Parity Error
R
R
R/W
Description
Indicates that a parity error has occurred during reception
in asynchronous mode and the reception ends
abnormally.
[Setting condition]
•
[Clearing condition]
•
Transmit End
[Setting conditions]
•
•
[Clearing conditions]
•
•
Multiprocessor Bit
Stores the multiprocessor bit value in the receive frame.
When the RE bit in SCR is cleared to 0 its previous state
is retained.
Multiprocessor Bit Transfer
Sets the multiprocessor bit value to be added to the
transmit frame.
When a parity error is detected during reception
Receive data when the parity error occurs is
transferred to RDR, however, the RDRF flag is not
set. Note that when the PER flag is being set to 1, the
subsequent serial reception cannot be performed. In
clocked synchronous mode, serial transmission also
cannot continue.
When 0 is written to PER after reading PER = 1
Even when the RE bit in SCR is cleared, the PER bit
is not affected and retains its previous value.
When the TE bit in SCR is 0
When TDRE = 1 at transmission of the last bit of a
transmit character
When 0 is written to TDRE after reading TDRE = 1
When a TXI interrupt request is issued allowing
DMAC or DTC to write data to TDR