DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 16

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 DMA Controller (DMAC)................................................................. 229
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Section 8 Data Transfer Controller (DTC)........................................................ 307
8.1
8.2
Rev.1.00 Sep. 08, 2005 Page xiv of xlviii
Features.............................................................................................................................. 229
Input/Output Pins............................................................................................................... 232
Register Descriptions......................................................................................................... 233
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
Transfer Modes .................................................................................................................. 254
Operations.......................................................................................................................... 255
7.5.1
7.5.2
7.5.3
7.5.4
7.5.5
7.5.6
7.5.7
7.5.8
7.5.9
7.5.10 Bus Cycles in Dual Address Mode ....................................................................... 283
7.5.11 Bus Cycles in Single Address Mode..................................................................... 292
DMA Transfer End ............................................................................................................ 297
Relationship among DMAC and Other Bus Masters ......................................................... 300
7.7.1
7.7.2
Interrupt Sources................................................................................................................ 302
Notes on Usage .................................................................................................................. 305
Features.............................................................................................................................. 307
Register Descriptions......................................................................................................... 309
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
DMA Source Address Register (DSAR) .............................................................. 234
DMA Destination Address Register (DDAR) ...................................................... 235
DMA Offset Register (DOFR).............................................................................. 236
DMA Transfer Count Register (DTCR) ............................................................... 237
DMA Block Size Register (DBSR) ...................................................................... 238
DMA Mode Control Register (DMDR)................................................................ 239
DMA Address Control Register (DACR)............................................................. 248
DMA Module Request Select Register (DMRSR) ............................................... 254
Address Modes ..................................................................................................... 255
Transfer Modes..................................................................................................... 259
Activation Sources................................................................................................ 264
Bus Access Modes................................................................................................ 266
Extended Repeat Area Function ........................................................................... 268
Address Update Function using Offset ................................................................. 271
Register during DMA Transfer............................................................................. 275
Priority of Channels.............................................................................................. 280
DMA Basic Bus Cycle.......................................................................................... 282
CPU Priority Control Function Over DMAC ....................................................... 300
Bus Arbitration among DMAC and Other Bus Masters ....................................... 301
DTC Mode Register A (MRA) ............................................................................. 310
DTC Mode Register B (MRB).............................................................................. 311
DTC Source Address Register (SAR)................................................................... 312
DTC Destination Address Register (DAR)........................................................... 313
DTC Transfer Count Register A (CRA) ............................................................... 313