DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 206

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller (BSC)
Rev.1.00 Sep. 08, 2005 Page 156 of 966
REJ09B0219-0100
Name
Chip select 0
Chip select 1
Chip select 2
Chip select 3
Chip select 4
Chip select 5
Chip select 6
Chip select 7
Wait
Bus request
Bus request
acknowledge
Bus request output
Data transfer
acknowledge 3
(DMAC_3)
Data transfer
acknowledge 2
(DMAC_2)
Data transfer
acknowledge 1
(DMAC_1)
Data transfer
acknowledge 0
(DMAC_0)
External bus clock
Symbol
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
WAIT
BREQ
BACK
BREQO
DACK3
DACK2
DACK1
DACK0
Bφ
I/O
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Strobe signal indicating that area 0 is selected
Acknowledge signal indicating that bus has been
External bus request signal used when internal bus
Function
Strobe signal indicating that area 1 is selected
Strobe signal indicating that area 2 is selected
Strobe signal indicating that area 3 is selected
Strobe signal indicating that area 4 is selected
Strobe signal indicating that area 5 is selected
Strobe signal indicating that area 6 is selected
Strobe signal indicating that area 7 is selected
Wait request signal when accessing external
address space.
Request signal for release of bus to external bus
master
released to external bus master
master accesses external address space in the
external-bus released state
Data transfer acknowledge signal for DMAC_3
single address transfer
Data transfer acknowledge signal for DMAC_2
single address transfer
Data transfer acknowledge signal for DMAC_1
single address transfer
Data transfer acknowledge signal for DMAC_0
single address transfer
External bus clock