DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 936

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 23 List of Registers
Rev.1.00 Sep. 08, 2005 Page 886 of 966
REJ09B0219-0100
Register Name
D/A data register 0
D/A data register 1
D/A control register 01
PPG output control register
PPG output mode register
Next data enable register H
Next data enable register L
Output data register H
Output data register L
Next data register H*
Next data register L*
Next data register H*
Next data register L*
Serial mode register_0
Bit rate register_0
Serial control register_0
Transmit data register_0
Serial status register_0
Receive data register_0
Smart card mode register_0
Serial mode register_1
Bit rate register_1
Serial control register_1
Transmit data register_1
Serial status register_1
Receive data register_1
Smart card mode register_1
A/D data register A
A/D data register B
A/D data register C
A/D data register D
A/D data register E
A/D data register F
A/D data register G
A/D data register H
Abbreviation
DADR0
DADR1
PCR
PMR
NDERH
NDERL
PODRH
PODRL
NDRH
NDRL
NDRH
NDRL
SMR_0
BRR_0
SCR_0
TDR_0
SSR_0
RDR_0
SCMR_0
SMR_1
BRR_1
SCR_1
TDR_1
SSR_1
RDR_1
SCMR_1
ADDRA
ADDRB
ADDRC
ADDRD
ADDRE
ADDRF
ADDRG
ADDRH
DACR01
8
8
8
8
8
8
Number
of Bits
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
16
16
16
Address
H'FFF76
H'FFF77
H'FFF78
H'FFF79
H'FFF7A
H'FFF7B
H'FFF81
H'FFF82
H'FFF83
H'FFF84
H'FFF85
H'FFF89
H'FFF8A
H'FFF8C
H'FFF8D
H'FFF90
H'FFF92
H'FFF98
H'FFF9C
H'FFF68
H'FFF69
H'FFF6A
H'FFF7C
H'FFF7D
H'FFF7E
H'FFF7F
H'FFF80
H'FFF86
H'FFF88
H'FFF8B
H'FFF8E
H'FFF94
H'FFF96
H'FFF9A
H'FFF9E
Module
D/A
D/A
D/A
PPG
PPG
PPG
PPG
PPG
PPG
PPG
PPG
PPG
PPG
SCI_0
SCI_0
SCI_0
SCI_0
SCI_0
SCI_0
SCI_0
SCI_1
SCI_1
SCI_1
SCI_1
SCI_1
SCI_1
SCI_1
A/D
A/D
A/D
A/D
A/D
A/D
A/D
A/D
Data
Width
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
16
16
16
16
16
16
16
16
2Pφ/2Pφ
Access
Cycles
(Read/Write)
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ
2Pφ/2Pφ