DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 168

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Interrupt Controller
(2)
The DTC activation source is selected according to the default priority, and the selection is not
affected by its mask level or priority level. For respective priority levels, see table 8.1, Interrupt
Sources, DTC Vector Addresses, and Corresponding DTCEs.
(3)
If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the
CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is
selected as the DTC or DMAC activation source or CPU interrupt source, respective operations
are performed independently.
Table 5.6 lists the selection of interrupt sources and interrupt source clear control by setting the
DTA bit in DMDR of the DMAC, the DTCE bit in DTCERA to DTCERH of the DTC, and the
DISEL bit in MRB of the DTC.
Table 5.6
[Legend]
√: The corresponding interrupt is used. The interrupt source is cleared.
O: The corresponding interrupt is used. The interrupt source is not cleared.
X: The corresponding interrupt is not available.
*: Don't care.
(4)
The interrupt sources of the SCI, and A/D converter are cleared according to the setting shown in
table 5.6, when the DTC or DMAC reads/writes the prescribed register.
To initiate multiple channels for the DTC with the same interrupt, the same priority (DTCP =
DMAP) should be assigned.
Rev.1.00 Sep. 08, 2005 Page 118 of 966
REJ09B0219-0100
DMAC Setting
DTA
0
1
(The interrupt source flag must be cleared in the CPU interrupt handling routine.)
Priority Determination
Operation Order
Usage Note
Interrupt Source Selection and Clear Control
DTCE
0
1
*
DTC Setting
DISEL
*
0
1
*
DMAC
O
O
O
√
Interrupt Source Selection/Clear Control
DTC
X
√
O
X
CPU
√
X
√
X