DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 366

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Data Transfer Controller (DTC)
Note:
Rev.1.00 Sep. 08, 2005 Page 316 of 966
REJ09B0219-0100
Bit
4
3
2, 1
0
*
Bit Name
RRS
RCHNE

ERR
Only 0 can be written to clear this flag.
Initial
Value
0
0
All 0
0
R/W
R/W
R
R/(W)* Transfer Stop Flag
R/W
Description
DTC Transfer Information Read Skip Enable
Controls the vector address read and transfer
information read. A DTC vector number is always
compared with the vector number for the previous
activation. If the vector numbers match and this bit is
set to 1, the DTC data transfer is started without
reading a vector address and transfer information. If the
previous DTC activation is a chain transfer, the vector
address read and transfer information read are always
performed.
0: Transfer read skip is not performed.
1: Transfer read skip is performed when the vector
Chain Transfer Enable After DTC Repeat Transfer
Enables/disables the chain transfer while transfer
counter (CRAL) is 0 in repeat transfer mode.
In repeat transfer mode, the CRAH value is written to
CRAL when CRAL is 0. Accordingly, chain transfer may
not occur when CRAL is 0. If this bit is set to 1, the
chain transfer is enabled when CRAH is written to
CRAL.
0: Disables the chain transfer after repeat transfer
1: Enables the chain transfer after repeat transfer
Reserved
These are read-only bits and cannot be modified.
Indicates that an address error or an NMI interrupt
occurs. If an address error or an NMI interrupt occurs,
the DTC stops.
0: No interrupt occurs
1: An interrupt occurs
[Clearing condition]
•
numbers match.
When writing 0 after reading 1