DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 36

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 14.9 Example of Operation for Transmission in Asynchronous Mode
Figure 14.10 Example of Serial Transmission Flowchart........................................................... 592
Figure 14.11 Example of SCI Operation for Reception
Figure 14.12 Sample Serial Reception Flowchart (1)................................................................. 595
Figure 14.12 Sample Serial Reception Flowchart (2)................................................................. 596
Figure 14.13 Example of Communication Using Multiprocessor Format
Figure 14.14 Sample Multiprocessor Serial Transmission Flowchart ........................................ 599
Figure 14.15 Example of SCI Operation for Reception
Figure 14.16 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 601
Figure 14.16 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 602
Figure 14.17 Data Format in Clocked Synchronous Communication (LSB-First)..................... 603
Figure 14.18 Sample SCI Initialization Flowchart ..................................................................... 604
Figure 14.19 Example of Operation for Transmission in Clocked Synchronous Mode ............. 606
Figure 14.20 Sample Serial Transmission Flowchart ................................................................. 606
Figure 14.21 Example of Operation for Reception in Clocked Synchronous Mode .................. 607
Figure 14.22 Sample Serial Reception Flowchart ...................................................................... 608
Figure 14.23 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 609
Figure 14.24 Pin Connection for Smart Card Interface .............................................................. 610
Figure 14.25 Data Formats in Normal Smart Card Interface Mode ........................................... 611
Figure 14.26 Direct Convention (SDIR = SINV = O/E = 0) ...................................................... 611
Figure 14.27 Inverse Convention (SDIR = SINV = O/E = 1) .................................................... 612
Figure 14.28 Receive Data Sampling Timing in Smart Card Interface Mode
Figure 14.29 Data Re-Transfer Operation in SCI Transmission Mode ...................................... 616
Figure 14.30 TEND Flag Set Timing during Transmission........................................................ 616
Figure 14.31 Sample Transmission Flowchart ........................................................................... 617
Figure 14.32 Data Re-Transfer Operation in SCI Reception Mode............................................ 618
Figure 14.33 Sample Reception Flowchart................................................................................. 619
Figure 14.34 Clock Output Fixing Timing ................................................................................. 619
Figure 14.35 Clock Stop and Restart Procedure......................................................................... 620
Figure 14.36 IrDA Block Diagram............................................................................................. 621
Figure 14.37 IrDA Transmission and Reception ........................................................................ 622
Figure 14.38 Sample Transmission using DTC in Clocked Synchronous Mode........................ 628
Figure 14.39 Sample Flowchart for Mode Transition during Transmission............................... 630
Figure 14.40 Port Pin States during Mode Transition
Rev.1.00 Sep. 08, 2005 Page xxxiv of xlviii
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 591
(Transmission of Data H'AA to Receiving Station A)........................................... 598
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) .............................. 600
(When Clock Frequency is 372 Times the Bit Rate) ............................................. 613
(Internal Clock, Asynchronous Transmission) ...................................................... 630
(Example with 8-Bit Data, Parity, One Stop Bit).................................................. 593