DF61654N50FTV Renesas Electronics America, DF61654N50FTV Datasheet - Page 750

• Manufacturer Part Number: DF61654N50FTV
• Description: IC H8SX/1654 MCU FLASH 120TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of DF61654N50FTV

• Core Processor: H8SX
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 75
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 120-TQFP, 120-VQFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)3DK1657 - DEV EVAL KIT FOR H8SX/1657
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 USB Function Module (USB)
15.10.4 Assigning Interrupt Sources to EP0
The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must
be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations.
15.10.5 Clearing the FIFO When DMA Transfer is Enabled
The endpoint 1 data register (EPDR1) cannot be cleared when DMA transfer for endpoint 1 is
enabled (EP1 DMAE in DMAR = 1). Cancel DMA transfer before clearing the register.
15.10.6 Notes on TR Interrupt
Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i,
EP2, or EP3.
The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent
from the USB host. However, at the timing shown in figure 15.24, multiple TR interrupts occur
successively. Take appropriate measures against malfunction in such a case.
Note: This module determines whether to return NAKC if the FIFO of the target EP has no data
Rev.1.00 Sep. 08, 2005 Page 700 of 966
REJ09B0219-0100
CPU
Host
USB
when receiving the IN token, but the TR interrupt flag is set after a NAKC handshake is
sent. If the next IN token is sent before PKTE of TRG is written to, the TR interrupt flag is
set again.
IN token
Determines whether
to return NACK
Figure 15.24 TR Interrupt Flag Set Timing
NACK
Sets TR flag
TR interrupt routine
Clear
TR flag
IN token
Determines whether
to return NACK
Writes
transmit data
NACK
TRG.
PKTE
Sets TR flag
(Sets the flag again)
TR interrupt routine
IN token
Transmits data
ACK