DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 100

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Table 2.1
Legend:
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-
Rev.7.00 Dec. 24, 2008 Page 46 of 698
REJ09B0074-0700
Function
Data transfer
Arithmetic
operations
Logic operations
Shift
Bit manipulation
Branch
System control
Block data transfer EEPMOV
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
5. ER7 is used as a stack pointer in STM and LDM instructions. ER7, therefore, should not
W: Word size
L: Longword size
B: Byte size
SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn,
@-SP.
be used as a saving (STM) or restoring (LDM) register.
Instruction Classification
Instructions
MOV
POP*
LDM*
MOVFPE*
ADD, SUB, CMP, NEG
ADDX, SUBX, DAA, DAS
INC, DEC
ADDS, SUBS
MULXU, DIVXU, MULXS, DIVXS
EXTU, EXTS
TAS*
AND, OR, XOR, NOT
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
Bcc*
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP
2
4
, JMP, BSR, JSR, RTS
5
1
, PUSH*
, STM*
3
, MOVTPE*
5
1
3
–
Size
B/W/L
W/L
L
B
B/W/L
B
B/W/L
L
B/W
W/L
B
B/W/L
B/W/L
B
–
–
Total: 65
5
8
1
Types
19
4
14
5
9