DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 22

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

2.8
2.9
Section 3 MCU Operating Modes
3.1
3.2
3.3
3.4
Section 4 Exception Handling
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Section 5 Interrupt Controller
5.1
5.2
5.3
Rev.7.00 Dec. 24, 2008 Page xxii of liv
REJ09B0074-0700
Processing States ............................................................................................................... 64
Usage Notes....................................................................................................................... 66
2.9.1
2.9.2
2.9.3
2.9.4
Operating Mode Selection................................................................................................. 71
Register Descriptions......................................................................................................... 72
3.2.1
3.2.2
Operating Mode Descriptions............................................................................................ 74
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
Memory Map in Each Operating Mode............................................................................. 77
Exception Handling Types and Priority ............................................................................ 81
Exception Sources and Exception Vector Table................................................................ 81
Reset .................................................................................................................................. 83
4.3.1
4.3.2
4.3.3
4.3.4
Traces ................................................................................................................................ 87
Interrupts ........................................................................................................................... 87
Trap Instruction ................................................................................................................. 88
Stack Status after Exception Handling .............................................................................. 89
Notes on Use of the Stack ................................................................................................. 90
Features ............................................................................................................................. 91
Input/Output Pins .............................................................................................................. 93
Register Descriptions......................................................................................................... 93
5.3.1
5.3.2
Note on TAS Instruction Usage ........................................................................... 66
STM/LTM Instruction Usage ............................................................................... 66
Note on Bit Manipulation Instructions ................................................................. 66
Accessing Registers Containing Write-Only Bits ................................................ 68
Mode Control Register (MDCR).......................................................................... 72
System Control Register (SYSCR) ...................................................................... 72
Mode 4 (Supported Only by the H8S/2218 Group).............................................. 74
Mode 5 (Supported Only by the H8S/2218 Group).............................................. 74
Mode 6 (Supported Only by the H8S/2218 Group).............................................. 75
Mode 7 ................................................................................................................. 75
Pin Functions........................................................................................................ 76
Reset Types .......................................................................................................... 83
Reset Exception Handling .................................................................................... 84
Interrupts after Reset ............................................................................................ 86
State of On-Chip Peripheral Modules after Reset Release ................................... 86
Interrupt Priority Registers A to G, J, K, M
(IPRA to IPRG, IPRJ, IPRK, IPRM) ................................................................... 94
IRQ Enable Register (IER)................................................................................... 95
........................................................................................... 91
.......................................................................................... 81
................................................................................... 71