DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 91

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

• Stack Structure
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In advanced mode the operand is a 32-bit longword operand,
providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is
regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
Note that the first part of this range is also the exception vector table.
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in exception handling, they are stored as shown in figure 2.4. When EXR
is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
SP
Notes: 1.
2.
3.
When EXR is not used, it is not stored on the stack.
SP when EXR is not used.
Ignored when returning.
(a) Subroutine Branch
Figure 2.4 Stack Structure in Advanced Mode
Reserved
(24 bits)
PC
( SP*
SP
2
Rev.7.00 Dec. 24, 2008 Page 37 of 698
)
(b) Exception Handling
(24 bits)
EXR*
Reserved*
CCR
PC
1
1
REJ09B0074-0700
*
3