DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 261

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

7.6
7.6.1
Except for forced termination, the operating (including transfer waiting state) channel setting
should not be changed. The operating channel setting should only be changed when transfer is
disabled. Also, the DMAC register should not be written to in a DMA transfer.
DMAC register reads during operation (including the transfer waiting state) are described below.
1. DMAC control starts one cycle before the bus cycle, with output of the internal address.
DMA Internal
address
DMA register
operation
DMA control
Consequently, MAR is updated in the bus cycle before DMAC transfer.
Figure 7.25 shows an example of the update timing for DMAC registers in dual address
transfer mode.
φ
Usage Notes
DMAC Register Access during Operation
[1]
[2]
[2']
[3]
Note:
Idle
Transfer source address register MAR operation (incremented/decremented/fixed)
Transfer counter ETCR operation (decremented)
Block size counter ETCR operation (decremented in block transfer mode)
Transfer destination address register MAR operation (incremented/decremented/fixed)
Transfer destination address register MAR operation (incremented/decremented/fixed)
Block transfer counter ETCR operation (decremented, in last transfer cycle of
a block in block transfer mode)
Transfer address register MAR restore operation (in block or repeat transfer mode)
Transfer counter ETCR restore (in repeat transfer mode)
Block size counter ETCR restore (in block transfer mode)
The MAR operation is post-incrementing/decrementing of the DMA internal address value.
[1]
Transfer
source
Read
Figure 7.25 DMAC Register Update Timing
[2]
DMA read
destination
DMA transfer cycle
Transfer
Write
DMA write
Idle
[1]
Rev.7.00 Dec. 24, 2008 Page 207 of 698
Transfer
source
Read
[2']
DMA read
DMA last transfer cycle
destination
Transfer
Write
DMA write
[3]
REJ09B0074-0700
Dead
DMA
dead
Idle