DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 487

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DF2211NP24V

Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag
set timing is shown in figure 12.30.
TDRE
TEND
FER/ERS
Figure 12.30 TEND Flag Generation Timing in Transmission Operation
Ds
I/O data
TXI
(TEND interrupt)
Transfer to TSR from TDR
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
When GM = 1
When GM = 0
Legend:
Ds:
D0 to D7:
Dp:
DE:
Figure 12.29 Retransfer Operation in SCI Transmit Mode
nth transfer frame
Start bit
Data bits
Parity bit
Error signal
Ds
D0
D1
D2
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
D3
Transfer to TSR from TDR
11.0 etu
12.5 etu
D4
Retransferred frame
D5
Rev.7.00 Dec. 24, 2008 Page 433 of 698
D6
D7
Dp
Guard
(DE)
time
DE
Ds D0 D1 D2 D3 D4
REJ09B0074-0700
Transfer to TSR
Transfer
frame n + 1
from TDR

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