DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 86

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DF2211NP24V

Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
• Two CPU operating modes
Note: * Normal mode is not available in this LSI.
• Power-down state
2.1.1
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
• Basic instructions
• The number of execution states of the MULXU and MULXS instructions
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.
Rev.7.00 Dec. 24, 2008 Page 32 of 698
REJ09B0074-0700
Instruction
MULXU
MULXS
⎯ 16 × 16-bit register-register multiply: 20 states
⎯ 32 ÷ 16-bit register-register divide: 20 states
⎯ Normal mode*
⎯ Advanced mode
⎯ Transition to power-down state by SLEEP instruction
⎯ CPU clock speed selection
The MAC register is supported only by the H8S/2600 CPU.
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
Differences between H8S/2600 CPU and H8S/2000 CPU
Mnemonic
MULXU.B Rs, Rd
MULXU.W Rs, ERd
MULXS.B Rs, Rd
MULXS.W Rs, ERd
H8S/2600
3
4
4
5
Execution States
H8S/2000
12
20
13
21

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