DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 656

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Table 19.4 External Clock Input Conditions when Duty Adjustment Circuit Is not Used
19.3
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
19.4
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32.
19.5
The bus master clock selection circuit selects the clock supplied to the bus master by setting the
bits SCK2 to SCK0 in SCKCR. The bus master clock can be selected from high-speed mode, or
medium-speed clocks (φ/2, φ/4, φ/8, φ/16, φ/32).
Rev.7.00 Dec. 24, 2008 Page 602 of 698
REJ09B0074-0700
Item
External clock input low pulse width
External clock input high pulse width
External clock rise time
External clock fall time
Duty Adjustment Circuit
Medium-Speed Clock Divider
Bus Master Clock Selection Circuit
EXTAL
t
EXr
Figure 19.5 External Clock Input Timing
Symbol
t
t
t
t
EXL
EXH
EXr
EXf
min
80
80
—
—
t
EXH
max
—
—
15
15
Min
31.25
31.25
—
—
t
EXf
t
EXL
max
—
—
6.25
6.25
min
20.8
20.8
—
—
V
CC
× 0.5
max
—
—
5.25
5.25
Unit
ns
ns
ns
ns
Test
Conditions
Figure 19.5