DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 368

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Table 9.18 PWM Output Registers and Output Pins
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set.
Example of PWM Mode Setting Procedure: Figure 9.21 shows an example of the PWM mode
setting procedure.
Rev.7.00 Dec. 24, 2008 Page 314 of 698
REJ09B0074-0700
Channel
0
1
2
Select counter clearing source
Select waveform output level
Select counter clock
Set PWM mode
Figure 9.21 Example of PWM Mode Setting Procedure
<PWM mode>
PWM mode
Start count
Set TGR
Registers
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0
in TCR.
Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
Set the cycle in the TGR selected in [2], and set
the duty in the other the TGR.
Select the PWM mode with bits MD3 to MD0 in
TMDR.
Set the CST bit in TSTR to 1 start the count
operation.
PWM Mode 1
TIOCA0
TIOCC0
TIOCA1
TIOCA2
Output Pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
PWM Mode 2
TIOCB2