DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 209

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

6.10
This LSI has a bus arbiter that arbitrates bus master operations.
There are two bus masters, the CPU and DMAC, which perform read/write operations when they
have possession of the bus. Each bus master requests the bus by means of a bus request signal. The
bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a
bus request acknowledge signal. The selected bus master then takes possession of the bus and
begins its operation.
6.10.1
The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master making the request. If there are bus requests from
more than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until that signal is canceled.
The order of priority of the bus masters is as follows:
An internal bus access by an internal bus master, and external bus release, can be executed in
parallel in the H8S/2218 Group.
In the event of simultaneous external bus release request, and internal bus master external access
request generation, the order of priority is as follows:
The H8S/2212 Group does not have the external bus release function.
6.10.2
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific times at which each bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DMAC,
the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of
the bus is as follows:
(High) DMAC > CPU (Low)
(High) External bus release > Internal bus master external access (Low)
Bus Arbitration
Operation
Bus Transfer Timing
Rev.7.00 Dec. 24, 2008 Page 155 of 698
REJ09B0074-0700