DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 636

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Rev.7.00 Dec. 24, 2008 Page 582 of 698
REJ09B0074-0700
Notes: 1.
2.
3.
4.
5.
Increment address
Pre-write (clearing data in the block to be erased to 0) isn not required.
x, y, z, α, β, γ, ε, η, θ, and N are shown in section 22.7, Flash Memory Characteristics.
Veryfy data is read in 16 bits.
Only 1 bit in the EBR register must be set. Two or more bits in EBR cannot be set.
Erasure is performed in block units. To erase multiple blocks, each block must be erased sequentially.
Figure 17.14 Erase/Erase-Verify Flowchart
No
No
Set block start address as verify address
H'FF dummy write to verify address
*5
Clear SWE1 bit in FLMCR1
Clear ESU1 bit in FLMCR1
Set SWE1 bit in FLMCR1
Clear EV1 bit in FLMCR1
Set ESU1 bit in FLMCR1
Clear E1 bit in FLMCR1
Set EV1 bit in FLMCR1
All erase block erased?
Last address of block?
Set E1 bit in FLMCR1
Verify data = all 1s?
Read verify data
End of erasing
Set EBR1 (2)
Disable WDT
Enable WDT
Wait (β) μs
Wait (η) μs
Wait (x) μs
Wait (y) μs
Wait (z) μs
Wait (
Wait (γ) μs
Wait (ε) μs
Wait (θ) μs
n = 1
Start
α
) μs
Yes
Yes
Yes
*1
*2
No
*2
*4
*2
*2
*2
*2
*2
*2
*3
Start erasing
Halt erasing
Clear SWE1 bit in FLMCR1
Clear EV1 bit in FLMCR1
Erase failure
Wait (η) μs
Wait (θ) μs
n ≥ (N)?
Yes
No
n ← n + 1
*2