DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 505

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

13.2
Table 13.1 shows the I/O pins used in the boundary scan function.
Table 13.1 Pin Configuration
Pin Name
TMS
TCK
TDI
TDO
TRST
Pin Configuration
I/O
Input
Input
Input
Output
Input
Function
Test Mode Select
Controls the TAP controller which is a 16-state Finite State
Machine.
The TMS input value at the rising edge of TCK determines the
status transition direction on the TAP controller.
The TMS is fixed high when the boundary scan function is not
used.
The protocol is based on JTAG standard (IEEE Std.1149.1).
This pin has a pull-up resistor.
Test Clock
A clock signal for the boundary scan function.
When the boundary scan function is used, input a clock of
50% duty to this pin.
This pin has a pull-up resistor.
Test Data Input
A data input signal for the boundary scan function.
Data input from the TDI is latched at the rising edge of TCK.
TDI is fixed high when the boundary scan function is not used.
This pin has a pull-up register.
Test Data Output
A data output signal for the boundary scan function. Data
output from the TDO changes at the falling edge of TCK. The
output driver of the TDO is driven only when it is necessary
only in Shift-IR or Shift-DR states, and is brought to the high-
impedance state when not necessary.
Test Reset
Asynchronously resets the TAP controller when TRST is
brought low.
The user must apply power-on reset signal specific to the
boundary scan function when the power is supplied. (For
details on signal design, refer to section 13.5, Usage Notes.)
This pin has a pull-up resister.
Rev.7.00 Dec. 24, 2008 Page 451 of 698
REJ09B0074-0700