DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 587

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

14.8.14 Pin Processing when USB Not Used
Pin processing should be performed as follows.
DrVCC = VCC, DrVSS = 0 V, USD+ = USD− = USPND = open state, VBUS = UBPM = 0 V
14.8.15 Notes on TR Interrupt
Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i,
EP1, or EP3.
The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent
from the USB host. However, at the timing shown in figure 14.30, multiple TR interrupts occur
successively. Take appropriate measures against malfunction in such a case.
Note: This module determines whether to return NAK if the FIFO of the target EP has no data
14.8.16 Clearing the FIFO when DMA Transfer Is Enabled
When DMA transfer is enabled (EP2T1 = 1 and EP2T0 = 0 or 1 in UDMAR) at endpoint 2, it is
not possible to clear OUTFIFO in EP2. It is necessary to disable DMA transfer (EP2T1 = 0 and
EP2T0 = 0 in UDMAR) before clearing the FIFO.
CPU
Host
USB
when receiving the IN token, but the TR interrupt flag is set only after a NAK handshake
is sent. If the next IN token is sent before PKTE of UTRG0 is written to, the TR interrupt
flag is set again.
IN token
Determines whether
to return NAK
Figure 14.30 TR Interrupt Flag Set Timing
NAK
Sets TR flag
TR interrupt routine
Clear
TR flag
IN token
Determines whether
to return NAK
Writes
transmit data
Rev.7.00 Dec. 24, 2008 Page 533 of 698
NAK
Sets TR flag
(Sets the flag again)
UTRG0/
PKTE
TR interrupt routine
IN token
Transmits data
REJ09B0074-0700
ACK