DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 337

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Table 9.8
Legend:
×: Don’t care
Notes: 1. MD3 is reserved bit. In a write, it should be written with 0.
Bit
4
3
2
1
0
Bit 3
MD3*
0
1
Bit Name Initial value
BFA
MD3
MD2
MD1
MD0
1
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.
MD3 to MD0
Bit2
MD2*
0
1
×
0
0
0
0
0
2
Bit 1
MD1
0
1
0
1
×
R/W
R/W
R/W
R/W
R/W
R/W
Description
Buffer Operation A
Specifies whether TGRA is to operate in the normal way,
or TGRA and TGRC are to be used together for buffer
operation. When TGRC is used as a buffer register,
TGRC input capture/output compare is not generated. In
channels 1 and 2, which have no TGRC, bit 4 is reserved.
It is always read as 0 and cannot be modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
Modes 3 to 0
These bits are used to set the timer operating mode.
MD3 is a reserved bit. In a write, the write value should
always be 0. See table 9.8, for details.
Bit 0
MD0
0
1
0
1
0
1
0
1
×
Description
Normal operation
Reserved
PWM mode 1
PWM mode 2
Phase counting mode 1
Phase counting mode 2
Phase counting mode 3
Phase counting mode 4
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Rev.7.00 Dec. 24, 2008 Page 283 of 698
REJ09B0074-0700