DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 738
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DF2211NP24V
Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
1.DF2211NP24V.pdf
(756 pages)
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22.8
General Notice during Design for Printed Circuit Board: Measures for radiation noise caused
by the transient current in this LSI should be taken into consideration. The examples of the
measures are shown below.
• To use a multilayer printed circuit board which includes layers for Vcc and GND.
• To mount by-pass capacitors (approximately 0.1 μF) between the Vcc and GND (Vss) pins,
Characteristics of F-ZTAT and Masked ROM Versions: Though the F-ZTAT version and the
masked ROM version satisfy electrical characteristics described in this manual, the actual value of
electrical characteristics, operating margin, and noise margin may differ due to the differences of
production process, on-chip ROM, and layout patterning.
When the system has been evaluated with the F-ZTAT version, the equivalent evaluation should
be implemented to the masked ROM version when shifted to the masked ROM version.
Rev.7.00 Dec. 24, 2008 Page 684 of 698
REJ09B0074-0700
and the PLLVcc and PLLGND pins, of this LSI.
3. Block erase time (Shows the total period for which the E1-bit FLMCR1 is set. It does not
4. Maximum programming time value
5. Maximum erasure time value
6. Minimum times that guarantee all characteristics after programming. (The guaranteed
7. Reference value when the temperature is 25°C. (It is reference that reprogramming is
8. Data hold characteristics when reprogramming is performed within the range of
Usage Note
include the erase verification time.)
t
range is 1 to the minimum value.)
normally enabled up to this value.)
specifications including the minimum value.
E
(max.) = Wait time after E1 bit set (z) × maximum erasure count (N)
t
p
(max.) = Wait time after P1 bit set (z) × maximum programming count (N1 + N2)
= (Z0 + Z2) × 6 + Z1 × 994
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