DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 128

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

3.3
3.3.1
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a data
bus, and part of port F carries bus control signals.
Pins P13 to P11 function as input ports immediately after a reset. Pin 10 and ports A and B
function as address (A20 to A8) outputs immediately after a reset. Address (A23 to A21) output
can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR)
regardless of the corresponding data direction register (DDR) values. Pins for which address
output is disabled among pins P13 to P10 and in ports A and B become port outputs when the
corresponding DDR bits are set to 1.
Port C always has an address (A7 to A0) output function.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-
bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.
3.3.2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Pins P13 to P10, and ports A, B, and C function as an address bus, ports D and E function as a data
bus, and part of port F carries bus control signals.
Pins P13 to P11 function as input ports immediately after a reset. Pin 10 and ports A and B
function as address (A20 to A8) outputs immediately after a reset. Address (A23 to A21) output
can be enabled or disabled by bits AE3 to AE0 in the pin function control register (PFCR)
regardless of the corresponding data direction register (DDR) values. Pins for which address
output is disabled among pins P13 to P10 and in ports A and B become port outputs when the
corresponding DDR bits are set to 1.
Port C always has an address (A7 to A0) output function.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if 16-
bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and
port E becomes a data bus.
Rev.7.00 Dec. 24, 2008 Page 74 of 698
REJ09B0074-0700
Mode 4 (Supported Only by the H8S/2218 Group)
Mode 5 (Supported Only by the H8S/2218 Group)
Operating Mode Descriptions