DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 173

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DF2211NP24V

Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
6.3.2
ASTCR designates each area as either a 2-state access space or a 3-state access space.
ASTCR sets the number of access states for the external memory space. The number of access
states for on-chip memory and internal I/O registers except for the on-chip USB is fixed regardless
of the settings in ASTCR.
Note: * The on-chip USB and on-chip RTC are allocated to area 6 and area 7, respectively.
Bit
7
6
5
4
3
2
1
0
Bit Name
AST7*
AST6*
AST5
AST4
AST3
AST2
AST1
AST0
Therefore, these bits should be set to 1.
Access State Control Register (ASTCR)
Initial Value R/W
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Area 7 to 0 Access State Control:
These bits select whether the corresponding area is to
be designated as a 2-state access space or a 3-state
access space. Wait state insertion is enabled or disabled
at the same time.
0: Area n is designated for 2-state access
1: Area n is designated for 3-state access
Legend: n = 7 to 0
Wait state insertion in area n external space is
disabled
Wait state insertion in area n external space is
enabled
Rev.7.00 Dec. 24, 2008 Page 119 of 698
REJ09B0074-0700

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