DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 388

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Contention between Buffer Register Write and Compare Match: If a compare match occurs in
the T
data prior to the write. Figure 9.48 shows the timing in this case.
Contention between TGR Read and Input Capture: If the input capture signal is generated in
the T
Figure 9.49 shows the timing in this case.
Rev.7.00 Dec. 24, 2008 Page 334 of 698
REJ09B0074-0700
2
1
state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the
state of a TGR read cycle, the data that is read will be the data after input capture transfer.
Figure 9.48 Contention between Buffer Register Write and Compare Match
φ
Address
Write signal
Compare
match signal
Buffer
register
TGR
φ
Address
Read signal
Input capture
signal
TGR
Internal
data bus
Figure 9.49 Contention between TGR Read and Input Capture
N
X
TGR write cycle
TGR read cycle
Buffer register
T
T
TGR address
1
1
address
M
T
T
2
2
M
M
N
Buffer register write data