DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 649
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DF2211NP24V
Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
1.DF2211NP24V.pdf
(756 pages)
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This LSI has an on-chip clock pulse generator that generates the system clock (φ), the bus master
clock, and internal clocks. The clock pulse generator consists of a main clock oscillator, duty
adjustment circuit, clock select circuit, medium-speed clock divider, bus master clock selection
circuit, subclock oscillator, waveform shaping circuit, PLL (Phase Locked Loop) circuit, and USB
operating clock selection circuit. A block diagram of clock pulse generator is shown in figure
19.1.
The frequency of the main clock oscillator can be changed by software by means of settings in the
low-power control register (LPWRCR) and system clock control register (SCKCR). PLL 48-MHz
clock can be selected by software by means of setting the USB control register (UCTLR). For
details, refer to section 14, Universal Serial Bus (USB).
CPG0600B_000020020900
EXTAL
XTAL
OSC1
OSC2
Legend:
LPWRCR: Low power control register
SCKCR:
UCTLR:
UCKS3 to UCKS0
oscillator
Subclock
oscillator
System clock control register
USB control register
clock
Main
selection circuit
operation
UCTLR
circuit
USB
clock
PLL
Figure 19.1 Block Diagram of Clock Pulse Generator
Section 19 Clock Pulse Generator
adjustment
LPWRCR
generation
Waveform
circuit
Duty
circuit
USB operation
48MHz
RFCUT
to USB
clock
RTC clock
to RTC
φ SUB
φ
selection
Clock
circuit
System clock
to φ pin
Rev.7.00 Dec. 24, 2008 Page 595 of 698
clock divider
Medium-
speed
Internal clock
to peripheral
modules
SCK2 to SCK0
φ/2
to φ/32
φ
selection
SCKCR
master
REJ09B0074-0700
circuit
clock
Bus
Bus master clock
USB clock
to USB
to CPU,
DMAC
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