DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 250

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

7.4.8
An example of the basic DMAC bus cycle timing is shown in figure 7.14. In this example, word-
size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the
bus is transferred from the CPU to the DMAC, a source address read and destination address write
are performed. The bus is not released in response to another bus request, etc., between these read
and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings.
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
Rev.7.00 Dec. 24, 2008 Page 196 of 698
REJ09B0074-0700
Basic DMAC Bus Cycles
CPU cycle
φ
Address bus
RD
HWR
LWR
Figure 7.14 Example of DMA Transfer Bus Timing
T
Source
address
1
T
DMAC cycle (1-word transfer)
2
T
1
Destination address
T
2
T
3
T
1
T
2
T
3
CPU cycle