DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 652

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Rev.7.00 Dec. 24, 2008 Page 598 of 698
REJ09B0074-0700
Bit
6
5
4
Bit Name Initial Value R/W
LSON
NESEL
SUBSTP 0
0
0
R/W
R/W
R/W
Description
Low Speed ON Flag
0: When the SLEEP instruction is executed in high-speed
1: When the SLEEP instruction is executed in high-speed
Noise Elimination Sampling Frequency Select
This bit selects the sampling frequency of the subclock
(φ
the clock (φ) generated by the system clock oscillator
0: Sampling using 1/32 x φ
1: Sampling using 1/4 x φ
Subclock Enable
This bit enables/disables subclock generation. This bit
should be set to 1 when subclock is not used.
0: Enables subclock generation.
1: Disables subclock generation.
SUB
mode or medium-speed mode, operation shifts to sleep
mode, software standby mode, or watch mode*.
When the SLEEP instruction is executed in subactive
mode, operation shifts to watch mode* or shifts directly
to high-speed mode.
Operation shifts to high-speed mode when watch mode
is cancelled.
mode*, operation shifts to watch mode or subactive
mode*.
When the SLEEP instruction is executed in subactive
mode, operation shifts to subsleep mode or watch mode.
Operation shifts to subactive mode when watch mode is
cancelled.
) generated by the subclock oscillator is sampled by