DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 95

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DF2211NP24V

Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
2.4.2
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is two bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0.)
2.4.3
EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
When these instructions except for the STC instruction is executed, all interrupts including NMI
will be masked for three states after execution is completed.
Bit
7
6 to 3 –
2
1
0
Bit Name
T
I2
I1
I0
Program Counter (PC)
Extended Control Register (EXR)
Initial Value R/W
0
All 1
1
SP (ER7)
R/W
R/W
Figure 2.8 Stack
Description
Trace Bit
When this bit is set to 1, a trace exception is generated
each time an instruction is executed. When this bit is
cleared to 0, instructions are executed in sequence.
Reserved
These bits are always read as 1.
These bits designate the interrupt mask level (0 to 7).
For details, refer to section 5, Interrupt Controller.
Rev.7.00 Dec. 24, 2008 Page 41 of 698
Free area
Stack area
REJ09B0074-0700

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