DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 595

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

15.4
ADDRA to ADDRD are 16-bit registers. As the data bus to the bus master is 8 bits wide, the bus
master accesses to the upper byte of the registers directly while to the lower byte of the registers
via the temporary register (TEMP).
Data in ADDR is read in the following way: When the upper-byte data is read, the upper-byte data
will be transferred to the CPU and the lower-byte data will be transferred to TEMP. Then, when
the lower-byte data is read, the lower-byte data will be transferred to the CPU.
When data in ADDR is read, the data should be read from the upper byte and lower byte in the
order. When only the upper-byte data is read, the data is guaranteed. However, when only the
lower-byte data is read, the data is not guaranteed.
Figure 15.2 shows data flow when accessing to ADDR.
Interface to Bus Master
Bus master
Bus master
(H'AA)
(H'40)
Read the upper byte
Read the lower byte
Figure 15.2 Access to ADDR (When Reading H'AA40)
Bus interface
Bus interface
ADDRnH
ADDRnH
(H'AA)
(H'AA)
Rev.7.00 Dec. 24, 2008 Page 541 of 698
Module data bus
ADDRnL
Module data bus
ADDRnL
TEMP
(H'40)
(H'40)
TEMP
(H'40)
(H'40)
(n = A to D)
(n = A to D)
REJ09B0074-0700