DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 366

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DF2211NP24V

Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
2. When TGR is an input capture register
Rev.7.00 Dec. 24, 2008 Page 312 of 698
REJ09B0074-0700
Figure 9.20 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC. Counter
clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have
been selected as the TIOCA pin input capture input edge. As buffer operation has been set,
when the TCNT value is stored in TGRA upon occurrence of input capture A, the value
previously stored in TGRA is simultaneously transferred to TGRC.
H'0F07
H'09FB
H'0532
H'0000
TIOCA
TGRA
TGRC
TCNT value
Figure 9.20 Example of Buffer Operation (2)
H'0532
H'0F07
H'0532
H'09FB
H'0F07
Time

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