DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 365

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Examples of Buffer Operation
1. When TGR is an output compare register
Figure 9.19 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in
this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B. As buffer operation has been set, when compare match A occurs
the output changes and the value in buffer register TGRC is simultaneously transferred to timer
general register TGRA. This operation is repeated each time compare match A occurs. For
details of PWM modes, see section 9.5.4, PWM Modes.
TGRB_0
TGRA_0
H'0000
TGRC_0
TGRA_0
TIOCA
TCNT value
Transfer
H'0200
H'0200
Figure 9.19 Example of Buffer Operation (1)
H'0200
H'0450
H'0450
Rev.7.00 Dec. 24, 2008 Page 311 of 698
H'0450
H'0520
REJ09B0074-0700
H'0520
Time