DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 115

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

2.7.8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode*, H'000000 to H'0000FF in advanced mode). In normal mode
the memory operand is a word operand and the branch address is 16 bits long. In advanced mode
the memory operand is a longword operand, the first byte of which is assumed to be H'00.
Note that the first part of the address range is also the exception vector area. For further details,
refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the least
significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the
address preceding the specified address. (For further information, see section 2.5.2, Memory Data
Formats.)
Note: * Not available in this LSI.
Memory Indirect—@@aa:8
Specified
by @aa:8
Figure 2.12 Branch Address Specification in Memory Indirect Mode
Note: * Normal mode is not available in this LSI.
(a) Normal Mode*
Branch address
Specified
by @aa:8
Rev.7.00 Dec. 24, 2008 Page 61 of 698
(b) Advanced Mode
Branch address
Reserved
REJ09B0074-0700