DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 394

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DF2211NP24V

Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
10.2
The WDT has the following three registers. For details, refer to section 21, List of Registers. To
prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to by a different
method to normal registers. For details, refer to section 10.5.1, Notes on Register Access.
• Timer counter (TCNT)
• Timer control/status register (TCSR)
• Reset control/status register (RSTCSR)
10.2.1
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 by a reset, when the
TME bit in TCSR is cleared to 0.
10.2.2
TCSR is an 8-bit readable/writable register. Its functions include selecting the clock source to be
input to TCNT, and selecting the timer mode.
Rev.7.00 Dec. 24, 2008 Page 340 of 698
REJ09B0074-0700
Register Descriptions
Timer Counter (TCNT)
Timer Control/Status Register (TCSR)
Internal reset signal*
(interrupt request
Legend:
TCSR:
TCNT:
RSTCSR:
Notes: When a sub-block is operating, φ will be φ
* The type of internal reset signal depends on a register setting.
signal)
WOVI
Timer control/status register
Timer counter
Reset control/status register
Figure 10.1 Block Diagram of WDT
RSTCSR
Interrupt
control
control
Reset
Overflow
Module bus
TCNT
Clock
SUB
WDT
.
Clock
select
TSCR
Internal clock
sources
interface
Bus
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072

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