DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 336

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Table 9.7
Note: This setting is ignored when channel 1 is in phase counting mode.
9.3.2
The TMDR registers are used to set the operating mode for each channel. The TPU has three
TMDR registers, one for each channel. TMDR register settings should be made only when TCNT
operation is stopped.
Rev.7.00 Dec. 24, 2008 Page 282 of 698
REJ09B0074-0700
Channel
2
Bit
7, 6
5
Bit Name
—
BFB
Timer Mode Register (TMDR)
TPSC2 to TPSC0 (channel 2)
Bit 2
TPSC2
0
1
Initial value
All 1
0
Bit 1
TPSC1
0
1
0
1
R/W
—
R/W
Description
Reserved
These bits are always read as 1 and cannot be modified.
Buffer Operation B
Specifies whether TGRB is to operate in the normal way,
or TGRB and TGRD are to be used together for buffer
operation. When TGRD is used as a buffer register.
TGRD input capture/output compare is not generation. In
channels 1 and 2, which have no TGRD, bit 5 is reserved.
It is always read as 0 and cannot be modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation
Bit 0
1
0
1
0
1
0
1
TPSC0
0
Internal clock: counts on φ/1
Internal clock: counts on φ/4
Internal clock: counts on φ/16
Internal clock: counts on φ/64
External clock: counts on TCLKA pin input
External clock: counts on TCLKB pin input
External clock: counts on TCLKC pin input
Internal clock: counts on φ/1024
Description