DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 104

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

Notes: 1. Size refers to the operand size.
Table 2.5
Note: * Size refers to the operand size.
Rev.7.00 Dec. 24, 2008 Page 50 of 698
REJ09B0074-0700
Instruction Size*
NEG
EXTU
EXTS
TAS*
Instruction Size*
AND
OR
XOR
NOT
2
B: Byte
W: Word
L: Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
B: Byte
W: Word
L: Longword
Logic Operations Instructions
B/W/L
W/L
W/L
B
B/W/L
B/W/L
B/W/L
B/W/L
1
Function
0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
@ERd – 0, 1 → (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
Function
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
∼ Rd → Rd
Takes the one's complement (logical complement) of general register
contents.
Rd (zero extension) → Rd
Rd (sign extension) → Rd