DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 142

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

4.6
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The trap instruction exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended control
2. The interrupt mask bit is updated and the T bit is cleared.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.5 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.5
Legend:
1: Set to 1
0: Cleared to 0
–: Retains value prior to execution.
Rev.7.00 Dec. 24, 2008 Page 88 of 698
REJ09B0074-0700
Interrupt Control Mode
0
2
register (EXR) are saved in the stack.
from the vector table to the PC, and program execution starts from that address.
Trap Instruction
Status of CCR and EXR after Trap Instruction Exception Handling
1
1
I
CCR
UI
–
–
I2 to I0
–
–
EXR
T
–
0