DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 490

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DF2211NP24V

Manufacturer Part Number
DF2211NP24V
Description
H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
Manufacturer
Renesas Technology / Hitachi Semiconductor
Datasheet
12.7.9
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and CKE1
in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure
12.34 shows the timing for fixing the clock output level. In this example, GM is set to 1, CKE1 is
cleared to 0, and the CKE0 bit is controlled.
Rev.7.00 Dec. 24, 2008 Page 436 of 698
REJ09B0074-0700
CKE0
SCK
Clock Output Control
No
Figure 12.33 Example of Reception Processing Flow
No
Figure 12.34 Timing for Fixing Clock Output Level
Specified pulse width
RDRF flag in SSR to 0
Read RDR and clear
All data received?
Clear RE bit to 0
ORER = 0 and
Start reception
Initialization
RDRF = 1?
PER = 0
Start
Yes
Yes
Yes
No
Specified pulse width
Error processing

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