DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 679

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

20.8
20.8.1
When the SLEEP instruction is executed with the SBYCR SSBY bit = 0, LPWRCR LSON bit = 1,
and TCSR_1 PSS bit = 1, CPU operation shifts to subsleep mode.
In subsleep mode, the CPU is stopped. Peripheral modules other WDT and RTC are also stopped.
The contents of the CPU's internal registers, the data in internal RAM, and the statuses of the
internal peripheral modules (excluding the A/D converter) and I/O ports are retained.
20.8.2
Subsleep mode is exited by an interrupt (interrupts from internal peripheral modules, NMI pin, or
IRQ0, to IRQ7), or signals at the RES, MRES*, or STBY pin.
• Exiting Subsleep Mode by Interrupts
• Exiting Subsleep Mode by RES or MRES* pin
• Exiting Subsleep Mode by STBY Pin
Note: * Supported only by the H8S/2218 Group.
When an interrupt occurs, subsleep mode is exited and interrupt exception processing starts.
In case of IRQ0, to IRQ7interrupts, subsleep mode is not cancelled if the corresponding enable
bit/pin function switching bit has been cleared to 0, and, in the case of interrupts from the
internal peripheral modules, the interrupt enable register has been set to disable the reception of
that interrupt, or is masked by the CPU.
For exiting subsleep mode by the RES or MRES* pin, see section 20.4.2, Clearing Software
Standby Mode.
When the STBY pin level is driven low, a transition is made to hardware standby mode.
Subsleep Mode
Transition to Sleep Mode
Exiting Subsleep Mode
Rev.7.00 Dec. 24, 2008 Page 625 of 698
REJ09B0074-0700