DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 527

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

14.3.4
UTRG0 is a one-shot register to generate triggers to the FIFO for each endpoint EP0 to EP3. For
details, see section 2.9.4, Accessing Registers Containing Write-Only Bits.
Bit
7, 6
5
4
3
2
1
Bit Name
—
EP2RDFN
EP1PKTE
EP3PKTE
EP0oRDFN 0
EP0iPKTE
USB Trigger Register 0 (UTRG0)
Initial Value R/W
All 0
0
0
0
0
R
W
W
W
W
W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
EP2 Read Complete
0: Performs no operation.
1: Writes 1 to this bit after reading data for EP2 OUT
EP1 Packet Enable
0: Performs no operation.
1: Generates a trigger to enable the transmission to
EP3 Packet Enable
0: Performs no operation.
1: Generates a trigger to enable the transmission to
EP0o Read Complete
0: Performs no operation.
1: Writes 1 to this bit after reading data for EP0o OUT
EP0i Packet Enable
0: Performs no operation.
1: Generates a trigger to enable the transmission to
FIFO. EP2 has a dual-FIFO configuration. This
trigger is generated to the currently effective FIFO.
EP1 IN FIFO. EP1 has a dual-FIFO configuration.
This trigger is generated to the currently effective
FIFO.
EP3 IN FIFO.
FIFO. This trigger enables EP0o to receive the
next packet.
EP0i IN FIFO.
Rev.7.00 Dec. 24, 2008 Page 473 of 698
REJ09B0074-0700