DF2211NP24V Renesas Technology / Hitachi Semiconductor, DF2211NP24V Datasheet - Page 484

• Manufacturer Part Number: DF2211NP24V
• Description: H8S/2200 Series, 2212 Group, USB, RTC, HSS TNP-64B; Vcc= 2.7 to 3.6 volts, Temp= -20 to 75 C; Package: PVQN0064LB-A
• Manufacturer: Renesas Technology / Hitachi Semiconductor

12.7.5
In Smart Card interface mode an internal clock generated by the on-chip baud rate generator can
only be used as a transmission/reception clock. In this mode, the SCI operates on a basic clock
with a frequency of 32, 64, 372, or 256 times the transfer rate (fixed to 16 times in normal
asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the
falling edge of the start bit using the basic clock, and performs internal synchronization. As shown
in figure 12.28, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or 128th pulse
of the basic clock, data can be latched at the middle of the bit. The reception margin is given by the
following formula.
M = | (0.5 –
Where M: Reception margin (%)
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
Rev.7.00 Dec. 24, 2008 Page 430 of 698
REJ09B0074-0700
N: Ratio of bit rate to clock (N = 32, 64, 372, and 256)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
= 49.866%
Receive Data Sampling Timing and Reception Margin
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
2N
Figure 12.28 Receive Data Sampling Timing in Smart Card Mode
1
) – (L – 0.5) F –
(Using Clock of 372 Times the Transfer Rate)
186 clocks
0
185
372 clocks
Start bit
| D – 0.5 |
N
371
(1+ F) | × 100 [%]
0
D0
185
371 0
D1